library ieee;
use ieee.std_logic_1164.all;

entity sram_aau is
  port (
    reset      : in    std_logic;
    clock      : in    std_logic;

    address    : in    std_logic_vector (17 downto 0);
    byteenable : in    std_logic_vector (1 downto 0);
    read       : in    std_logic;
    readdata   : out   std_logic_vector (15 downto 0);
    write      : in    std_logic;
    writedata  : in    std_logic_vector (15 downto 0);

    sram_addr  : out   std_logic_vector (17 downto 0);
    sram_dq    : inout std_logic_vector (15 downto 0);
    sram_we_n  : out   std_logic;
    sram_oe_n  : out   std_logic;
    sram_ub_n  : out   std_logic;
    sram_lb_n  : out   std_logic;
    sram_ce_n  : out   std_logic
  );
end entity sram_aau;

architecture default of sram_aau is
  signal wr_reg     : std_logic;
  signal wr_dat_reg : std_logic_vector (15 downto 0);
begin

  process (reset, clock)
  begin
    if reset = '1' then
      readdata <= (others => 'Z');

      sram_addr <= (others => '0');
      sram_we_n <= '1';
      sram_oe_n <= '1';
      sram_ub_n <= '1';
      sram_lb_n <= '1';
      sram_ce_n <= '1';
    elsif rising_edge (clock) then
      readdata <= sram_dq;

      sram_addr <= address;
      sram_lb_n <= not (byteenable (0));
      sram_ub_n <= not (byteenable (1));
      sram_ce_n <= not (read or write);
      sram_oe_n <= not (read);
      sram_we_n <= not (write);
    end if;
  end process;

  process (reset, clock)
  begin
    if reset = '1' then
      wr_reg <= '0';
      wr_dat_reg <= (others => '0');
    elsif rising_edge (clock) then
      wr_reg <= write;
      wr_dat_reg <= writedata;
    end if;
  end process;

  sram_dq <= wr_dat_reg when (wr_reg = '1') else (others => 'Z');

end architecture default;
